1. Field of the Invention
This invention is related to integrated circuit design methodology and, more particularly, to ensuring testability of the integrated circuit in manufacture.
2. Description of the Related Art
As semiconductor fabrication technology continues to reduce the size of transistors fabricated on an integrated circuit “chip,” the number of transistors included on a given integrated circuit continues to increase. The increase in the number of transistors increases the likelihood that a given instance of the integrated circuit may have a manufacturing flaw that prevents the integrated circuit from operating as designed. Additionally, the reduced size of the transistors also decreases the minimum size of a flaw that can cause incorrect operation.
To avoiding shipping a flawed integrated circuit to a customer, various schemes to test the integrated circuit during manufacturing (e.g. at the foundry which implements the fabrication process) are often used. For example, scan testing can be used to detect flaws that cause a given signal in the integrated circuit to be “stuck at” a given binary value (i.e. the signal is unable to switch to the opposite binary value even when the circuitry generating the signal should logically cause such a switch). Such scan testing is typically performed at a relatively low clock frequency (e.g. compared to the clock frequency at which the integrated circuit will operate). Another type of scan testing is transition testing, which tests if transitions in the logic state in a clocked storage device (such as a flop) can propagate through the logic circuitry to be captured at a receiving clocked storage device. Transition testing is typically conducted at expected operating frequencies (although the shifting portion of the test can be conducted at lower frequencies).
An additional issue that requires analysis in the design of integrated circuits is the integrity of the power supply. As the number of transistors in the integrated circuit increases, the potential for power supply droop to be an issue increases as well. That is, the impedance characteristics of the power supply distribution interconnect in the integrated circuit, and even the package impedance effects, coupled with localized high current loads due to switching can cause local droop in the magnitude of the supply voltage. Such droops can slow the operation of the circuitry, and even cause functional failure. Testing for such voltage droop conditions is referred to as instance voltage drop (IVD) testing.
Scan testing typically involves shifting a pattern of binary zeros and ones into the clocked storage devices of the integrated circuit, clocking one or more functional clocks to capture state change in the clocked storage devices, and shifting out the captured state to compare against expected state. The testing operations can cause switching noise and voltage droop on the power supply, since the circuitry connected to the clocked storage devices reacts to the shifting states. In some cases, the voltage droop can be severe enough that incorrect operation occurs. If incorrect operation occurs due to voltage droop, then the circuitry that experiences the voltage droop cannot be tested successfully.
The procedures to generate the test patterns for scan testing are long latency, and thus are typically only performed at or near tapeout of an integrated circuit design, when the scan chains are essentially finalized. Once the test patterns (also called “test vectors”) are generated, the vectors may be applied to the circuit design in a power integrity tool to check for IVD issues. Accordingly, IVD testing often occurs months after the tapeout, when it is no longer possible to make changes to the current integrated circuit design. Changes must wait for a subsequent tapeout, or in the case that the tapeout is for production, changes are no longer possible for that design.
An exemplary power integrity tool may be the RedHawk™ tool from Apache Design Solutions, Inc. (San Jose, Calif.). The RedHawk™ tool supports vector-based IVD analysis using the above test vectors. The RedHawk™ tool also supports a vectorless mode in which the tool analyzes IVD without test vectors. However, the vectorless mode required input and changes from the inventor of this application in order to work correctly for the methodology described below.